General Introduction
Logic Analyzers are members of a class of electronic test equipment that observes collections of digital signals, converts them to instances of corresponding logic values along a time axis, and reports on and analyzes their (logical) activity. This class of test equipment, which we may call data analysis equipment, generally samples only once within each consecutive UI (Unit Interval) or period, takes the sampled value as indicative of the logical value for that UI (through threshold comparison), and does not attempt to reconstruct the underlying analog waveform. A clock signal is either re-constructed from the data or is supplied as a separate signal, and transitions in the clock signal are used to delimit the UI. As the speeds of digital systems increase into the Gigabit per second region the issues of exactly where within the UI to make the threshold decision for a data signal (“delay”), and with what threshold voltage, become increasingly problematic. Quite aside from how the SUT (System Under Test) itself performs these tasks, the Logic Analyzer has to perform them as well, and do so correctly if the measurement of the data is to have any utility. It is conventional for both the threshold and the delay relative to the onset of the UI (as indicated by a transition in the clock signal) to be adjustable by the operator of the Logic Analyzer. Hereinafter, we shall collectively refer to these as ‘sampling parameters’ and to their individual elements as ‘threshold’ and ‘sample position,’ respectively. Some Logic Analyzers even attempt to automate the process of selecting these sampling parameters. These prior art techniques for setting threshold and sample position each have certain associated disadvantages.
An eye diagram is a stylized representation of a signal's behavior. An eye diagram can be made by superimposing a large number of time domain trace segments that each correspond to just an individual UI. Implicit in this idea is the notion that satisfaction of some trigger event (related to the clock signal) allows the correct registration of each segment on the other. This will display both rising and falling edges, and asserted regions (whether HIGH or LOW) each in their same relative horizontal locations, for perhaps a million (or more) cycles of the signal. The result is (hopefully) a central empty opening called an ‘eye’ (on account of its shape) that is free of any traced activity, since during that time any signal will be either already HIGH or already LOW. At each edge of an eye for a typical (non-pulse) signal is an X-shaped boundary produced by rising and falling transitions, with straight lines above and below the Xs produced by the various consecutive ONEs and consecutive ZEROs in the data. And while it is then possible to discern if in that collection of cycles there were instances of overshoot, slow rise or fall times, or inappropriate asserted voltage levels, knowledge about which cycle(s) is(are) at fault is generally lost. That is a minor price to pay for an easily viewed presentation that gives valuable information about overall margins (the size and shape of the eye). Once any such violations of margins are confirmed, their location in the data (if such information is needed) and their causes can be sought using other test techniques.
For data analysis equipment, such as Logic Analyzers, that capture the logical values once per UI (as opposed to a ‘scope that densely samples the actual analog waveform), it is conventional to use the ‘X crossing’ voltage of an eye diagram as the threshold for a data receiver (comparator), and to delay the capture of the comparison output from the associated clock so as to locate the sample position midway between consecutive crossings. However, this may not actually be an optimum set of sampling parameters. Consider first the matter of threshold voltage. Unlike its brother the DSO (Digital Sampling Oscilloscope) that simply digitizes a waveform and reconstructs it afterward, the Logic Analyzer relies upon a threshold comparator (often called a ‘receiver’) to decide what the logic value is. So does the SUT. But a receiver can require forty or fifty millivolts of abrupt signal excursion to reliably transition with equal delays in each direction. That may translate to two hundred and fifty millivolts at the input to a passive isolation network at which the signal is actually applied. This is a required amount of signal excursion, called ΔVmin. There is also a required minimum pulse duration called ΔTmin that needs to be applied before the output will reliably switch from one state to the other. Half a nanosecond is a reasonable example value for minimum signal duration.
So, when we consider where in an eye opening to locate sampling parameters for best Logic Analyzer operation (or more generally, for best operation of a particular data receiver in whatever kind of equipment) we ought to keep the required minimum voltage excursion ΔVmin and its required minimum duration ΔTmin in mind. Particularly so, if the shape of the eye opening for the applied signal is less than ideal.
Accordingly, another way to define the degree to which a combination of sampling parameters is satisfactory is to take into account the performance requirements of the receiver that is in use, and choose a location that offers equal margins in all directions (i.e, for both directions in each of voltage and in time). This sounds harmless enough, but can be difficult to accurately visualize, particularly if the eye diagram for the signal of interest differs significantly from an ideal or nominally correct shape. Say, for example, the signals of interest arrive over transmission lines that are beset with reflections. This condition can give the eye opening a stepped contour or ringing at one end, and to maximize the ability of the Logic Analyzer (or a receiver in other equipment) to sample correctly we may wish to deliberately move, say, the location of the sample position within the time duration of the UI to gain better access to the ΔVmin required of the signal. The presence of jitter is another factor that affects the situation. But we realize that in changing the sample position we are trading increased voltage margin for a decrease in margin for pulse width. It is not so easy to tell by simple observation where the gain in one parameter's margin begins to erode the minimum margin needed for the other. This is particularly so if the eye diagram has signal occurrences for regions INTERIOR to the nominal eye opening. This last business of signal activity indicated within the nominal eye opening, when combined with different rate of margin consumption versus changes in the sampling parameters, can REALLY complicate the task of finding suitable sampling parameters.
Recently, some data analysis equipment, including Logic Analyzers, have begun to support the ability to perform eye diagram measurements, and new techniques are thus possible within an instance of such test equipment (such as Logic Analyzers) to allow it to automatically recommend or decide the best time within the UI, and with what threshold, to ‘sample’ an incoming signal to decide its logical value. Such automatic selection (or a recommendation) should take the behavior of the data receiver into account and can be of benefit to the internal operation of the Logic Analyzer when used in its traditional logic analysis capacity (it is desirable that it not mis-sample the data . . . ). In addition, such recommended information (not necessarily obtained from a Logic Analyzer, but perhaps from a ‘scope that also does eye diagrams) can also be of use to persons responsible for setting the sampling parameters for the receivers that belong to/are part of the SUT itself, and that are not part of any external test equipment, such as Logic Analyzer.
In the material that follows we shall use the term ‘signal’ in its usual way (as observable electrical behavior on a conductor), and usually use the term ‘channel’ when both a signal and its associated data receiver is meant. Functionally, the two terms are frequently equivalent and often interchangeable.